Ive read everywhere that the post T&L cache is "FIFO" but Im not sure how to interpret this. Does it mean that for a list like 4,5,6,7,8 the GPU can only access the element "4", or does it mean that all elements in the cache can be accessed, but if a new element is added(like 9), then the element "4" will be the one pushed out of the cache?
And whats the size of that cache today on an average card(PC) ? 10? 20?
I want to draw lots of NxN grids from triangles. ....using drawElements, triangle strips, static draw. I guess within a grid after every row I should change the direction of the draw(so after a left-to-right row I do a right-to-left row) so I get more cache hits. ....and I would like to know whats the "ideal" N number for this?