I just wanted to give some comments on the explicit uniform business and the layout for outs of a vertex shader

the following (dumb and bad names) shaders fed to NV driver:

vertex shader:
Code :
struct giggles
  float f1[4];
  vec4 ff;
  mat4 tt;
uniform float g;
uniform mat4 matrix;
uniform float f;
uniform float ggs[4];
uniform struct giggles more_bad_names;
layout(location=0) in vec4 vert;
layout(location=3) in vec2 tex;
layout(location=1) out vec2 ftex;
layout(location=2) out vec2 gtex;
  for(int i=0;i<4;++i)
  gl_Position=matrix*(f*vert +more_bad_names.tt*more_bad_names.ff);

fragment shader:
Code :
layout(location=1) in vec2 ftex;
layout(location=2) in vec2 gtex;
out vec4 color;
uniform sampler2D sl;
uniform float ss;
  color=ss*texture(sl, ftex);

work fine under nVidia, notice that assigning of location to the outs of a vertex shader and same values as ins of a fragment shader.

Using the same location twice in the vertex shader on a varying gives the error: (in this case using 2 twice)

0(23) : error C5121: multiple bindings to output semantic "ATTR2"
where as in the fragment shader no error is reported (I guess that means the two in's are sourced from the same place). Also no error is reported if the layouts don't match.

Also, the output for the locations of the uniforms is instructive:

0: f
1: g
2: ggs
6: matrix
7: more_bad_names.f1
11: more_bad_names.ff
12: more_bad_names.tt
13: sl
14: ss
notice that a mat4 takes only one uniform slot, although it is 16 floats. People with ATI hardware, can you try the above shader pair out? (most likely remove the layout on vertex outs and fragment ins though).

Later I will make a better shader pair to see if the location for vert outs actually has an effect... that and see if EXT_seperate_shader_object is ok if one specifies the locations of (outputs of vertex shaders)/(inputs of fragment shaders) under NV.

Hmm.. this is kind of off topic now... maybe a new thread somewhere else for this? Though this is now walking to undocumented behavior land though.