VAR Weirdness and Write Combining

[JelloFish]

1st Question:
I'm having some problems getting var to work with my system. Basically I am switching my memory to be allocated by the wglAllocateMemoryNV function, then I am calling glVertexArrayRangeNV then glEnableClientState(GL_VERTEX_ARRAY_RANGE_NV);, afterword everything is left as normal. But alas all the vertices are jumbled. What kind of VAR mistake could cause this?

2nd Question:
What chipsets can write combine to multiple arrays?(I read previously P3's but do athalons as well?)
As well can you obtain writecombing with a loop such that
for all verticies
{
perform an action
write result to VAR array
}
Is there a good document on the web about the best techniques to do write combining?

[jwatte]

If your vertex data is jumbled, you're generating it wrong. Try doing the EXACT same code, but call malloc() instead of AllocateMemory(), and don't enable/establish the vertex array range. I'm really meaning comment out those three lines, and copy the AllocateMemory line to a malloc() call, so you know that's the ONLY difference. Then see if the data is still jumbled.

Regarding write combining: there are very limited write combining resources on any chip. On a pentium III, any L1 cache miss is likely to cause contention for write combiner resources, and the CPU is really quite willing to partially evict your half-written line so that it can move an L2 cache line closer to the CPU.

Thus, pre-touch all data you will need for a block of verts, so that it's all in L1. THEN write-combine out, making sure you overwrite ENTIRE cache line aligned blocks.

[Devulon]

I know AMD has a really good article on a variety of different prefetch methods. THe obvious, using PREFETCH commands with assembly as well as C code to trick/convince the processor to load multiple cache lines with your data. Its on the AMD website in the developer section. I don't know exactly where but dig around and you should be able to find it. I would like to think that most of the non AMD specific methods would work quite well on Pentiums. The architecture really is quite similar. I definately think that the C version of cache loading will work almost exactly the same on Intel. I am sure Intel has equivalent documents as well. I know they did a while back but its been a while since I have been to there website.

Hope this helps.

Devulon

[JelloFish]

If I allocate memory using var but dont enable var, everything seems to render correctly. (Just really slowly)

[knackered]

Are you changing the vertices every frame?

[JelloFish]

Several times per frame. I am calling every form of flush before the data is written the second time(untill I get fence going). Interestingly enough the render is less jumbled when the flushes are then compared to without. And when I say jumbled I mean some faces are there some aren't. None of the faces have the correct texture coordinates. Some faces are going off into infinity. ext.

[jwatte]

1. PREFETCH has absolutely nothing to do with write combining.


2. Are you sure you enable the VAR correctly? Specifically, VertexArrayRange() takes a number of BYTES as parameter, whereas most other GL operations operate on larger units (pixels, vertices, what have you).

[knackered]

If you're not using fences, then just glDisable(GL_VERTEX_ARRAY_RANGE) every frame, which flushes the VAR stuff as a side effect.
You really should use a fence though (and when you do use a fence, and want to disable VAR every frame, use glDisable(GL_VERTEX_ARRAY_RANGE_WITHOUT_FLUSH); )

[wimmer]

Try to align all your arrays on 32 byte boundaries and let me know whether that works. I had a similar problem once, and this fixed it for me.

Michael

[JelloFish]

That was it! Thanks.

Where is that documented anyways?